1. Field of the Invention
The present invention relates to semiconductor devices and, more specifically, to a structure of a capacitor suitable for increasing capacity in a semiconductor device having a so-called stacked type capacitor, and to a method of manufacturing the same.
2. Description of the Background Art
A DRAM (Dynamic Random Access Memory) is one of semiconductor devices or semiconductor memory devices capable of random input/output of memory information. The DRAM comprises a memory cell array serving as a memory region for storing a number of pieces of information, and a peripheral circuit portion for executing prescribed input/output operations to and from the memory cell array. The memory cell array comprises a plurality of memory cells arranged, each serving as a minimum memory unit. The memory cell is basically formed by one capacitor and one transfer gate transistor connected thereto. In operation, whether or not prescribed charges are stored in the capacitor is determined, and the stored information is processed by data"0" or "1" corresponding to the result of determination.
FIG. 9D is a cross sectional view of a memory cell of a conventional DRAM. The DRAM is disclosed in, for example, Japanese Patent Laying-Open No. 64-42161. The memory cell of the DRAM shown in FIG. 9D has a so-called 1 transistor 1 capacitor type cell structure. The transfer gate transistor 10 comprises a pair of n.sup.+ impurity regions 3a and 3b formed on the surface of a p type silicon substrate 1, and a gate electrode 5a formed on the surface of the silicon substrate 1 positioned between the n.sup.+ impurity regions 3a and 3b with a thin gate insulating film 4 posed therebetween. The gate electrode 5a is formed by a part of a word line. The circumference of the gate electrode 5a is covered by a first interlayer insulating layer 30. The capacitor 20 comprises a lower electrode (storage node) 21 connected to one n.sup.+ impurity region 3a, a dielectric layer 22 covering the surface of the lower electrode 21 and an upper electrode (cell plate) 23 covering the surface thereof. A bit line 7 is connected to the n.sup.+ impurity region 3b through a contact hole formed in a second interlayer insulating layer 31.
As the degree of integration of semiconductor devices has been increased recently, each of the elements of this type of DRAM must be reduced in size. Accordingly, in such a memory cell as shown in FIG. 9D, planar area of occupation of the capacitor 20 must be reduced. In this circumstance, mainly two methods have been proposed to surely provide prescribed electrostatic capacitance necessary for the operation of the capacitor of the memory cell.
The first method is to increase electrostatic capacitance by making thinner the dielectric layer 22 constituting the capacitor 20. For example, in a DRAM having the degree of integration of 1 M bit, the dielectric layer 22 is made as thin as about 10 nm in silicon oxide film equivalent. Therefore, it is difficult to make this layer thinner when the degree of integration is further increased.
The second method is to surely maintain electrostatic capacitance by increasing opposing area between the electrodes 21 and 23 opposing to each other with the dielectric layer 22 posed therebetween. A capacitor formed in accordance with this method is called a stacked type capacitor. More specifically, a polycrystalline silicon layer having conductivity is formed on a surface of a diffusion layer in the semiconductor substrate, and the dielectric layer and the second electrode layer are stacked on the surface of the silicon layer. Various stacked type capacitors in which the electrode layer formed of polycrystalline silicon has a fin structure, a cylindrical shape and the like have been proposed.
As a modification of the second method, a method of forming concaves and convexes on the surface of the lower electrode to increase the opposing area of the capacitor has been proposed. The memory cell shown in FIG. 9 comprises a capacitor having the lower electrode 21 with concaves and convexes formed on the surface thereof. FIGS. 9A to 9D are cross sectional views showing the steps of manufacturing such a memory cell of the DRAM in this order. The manufacturing method will be described in the following with reference to the figures.
Referring to FIG. 9A, a field oxide film 2 of thin silicon oxide film is formed by LOCOS method on a prescribed region on a surface of a p type silicon substrate 1. Then a gate oxide film 4 is formed on the surface of the p type silicon substrate by thermal oxidation. A polycrystalline silicon layer is deposited on the entire surface by CVD method, and a gate electrode 5a is formed by patterning. Then a silicon oxide film is deposited on the entire surface of the p type silicon substrate 1 by low pressure chemical vapor deposition, and a first interlayer insulating layer 30 is formed on the surface and on the side surfaces of the gate electrode 5a by known lithography and dry etching. Then n.sup.+ impurity regions 3a and 3b are formed by ion implantation of impurities to the p type silicon substrate 1 with the gate electrode 5a covered by the interlayer insulating layer 30 serving as a mask.
Then, referring to FIG. 9B, a polycrystalline silicon layer 210 having the thickness of 0.4 .mu.m is formed by low pressure CVD method using monosilane gas diluted to 20% by helium. The pressure is set at 0.8 Torr and the temperature is 680.degree. C. The polycrystalline silicon layer 210 manufactured by this step has concaves and convexes of about 0.07 .mu.m on the surface thereof. Then are introduced to the polycrystalline silicon layer 21 by thermal oxidation using phosphorus oxychloride (POCl.sub.3) as a material, at 875.degree. C. for 30 minutes. After phosphor glass formed on the surface of the polycrystalline silicon layer 210 during thermal diffusion is removed, thermal processing is carried out in nitrogen at 900.degree. C. for 20 minutes. Consequently, the concaves and convexes on the surface of the polycrystalline silicon layer are enlarged to 0.11 .mu.m.
Referring to FIG. 9C, the polycrystalline silicon layer 210 is patterned by photolithography and etching to form a lower electrode 21 of the capacitor. Then a thermal nitride film is formed on the surface of the lower electrode 21, a silicon nitride film is formed by CVD method on the surface thereof, and a thermal oxide film is formed by thermal oxidating further thereon. Consequently, a dielectric layer 22 comprising three layers of thermal oxide film/CVD silicon nitride film/silicon oxide film is formed.
Then, referring to FIG. 9D, a polycrystalline silicon layer is formed entirely on the surface of the p type silicon substrate 1 and it is patterned to have a prescribed shape. Consequently, an upper electrode 23 of the capacitor 20 is formed. Then a second interlayer insulating film 31 of thick oxide film is formed on the entire surface. A contact hole is formed at a prescribed region of the interlayer insulating layer 31 and a bit line 7 is formed therein.
The memory cell of the DRAM is completed through the above described steps. The above described example is one of the means for solving the same problem to be solved by the present invention described later. This method is effective in surely providing prescribed electrostatic capacitance of a capacitor used in an integrated circuit whose degree of integration is to be increased.